InP DHBT Linear Modulator Driver With a 3-Vppd PAM-4 Output Swing at 90 GBaud: From Enhanced Transistor Modeling to Integrated Circuit Design

In this article, we report on the modeling, design, and characterization of indium phosphide (InP) double heterojunction bipolar transistor (DHBT) devices integrated circuits (ICs) for next-generation optical communications. Critical aspects transistors’ modeling their influence IC design are detailed, as well a lumped linear modulator driver featuring 3-Vppd four-level pulse-amplitude modulation (PAM-4) output swing at 90 GBaud (GBd). particular, propose an electromagnetic (EM) simulation-based parasitic extraction method DHBT access structures, to refine performance prediction accuracy. It is shown provide better estimation canonical cascode gain $\mu$ stability factor millimeter-wave frequencies, in 50–110 GHz frequency range. Furthermore, high-frequency boosting (self-peaking) topology, based upon emitter-degenerated paralleled-transistor configuration, analyzed using simplified model leveraged enhance output-stage gain–bandwidth product with controlled amount peaking gain. This self-peaking technique be inherent structures can therefore used other technologies, no added complexity. The was implemented 0.5- m InP-DHBT technology features bandwidth excess 110 GHz, 13 dB 95 GHz. Besides, it achieves 9.1-dBm single-ended power 1 compression 2.7% root-mean-square total harmonic distortion (rms-THD) swing. consumption 0.67 W, which among lowest state art shows 1.5-GBd figure merit (FoM). To best our knowledge, highest notation="LaTeX">$\geq$ 64 GBd PAM-4 performances reported date, without digital signal processing (DSP) or postprocessing.